1. Field of the Invention
Apparatuses and methods consistent with the present invention relate to frequency synthesis, and more particularly, to fractional-N frequency synthesis using a sigma-delta modulation.
2. Description of the Related Art
Recently, there are increasing demands for real-time multimedia data services from users who utilize wireless communications. That is, users desire to not only access Internet at high data rate but also receive video data in real-time using mobile communication terminals.
In response to this trend, code division multiple access (CDMA) 2000 currently developed allows high-speed data services at 144 kbps which is a conventional CDMA band. A frequency synthesizer, which is used for the high-speed data services, needs to satisfy a setting time under 500 μs, an accurate frequency resolution at intervals of 10 kHz, and a phase noise below −135 dBc/Hz around 1 MHz offset frequency all together. Particularly, to meet the requirement of the setting time under 500 μs, the frequency synthesizer has a phase-locked-loop (PLL) bandwidth more than 10 kHz at minimum.
Typically, integer-N frequency synthesizers are widely used in mobile communication systems such as CDMA. The integer-N frequency synthesizer is subject to a structural constraint that a reference frequency should match a channel bandwidth. The channel bandwidth of a frequency synthesizer can be defined as a frequency resolution for selecting an accurate channel. In other words, the channel bandwidth lower than 30 kHz and 10 kHz, respectively should be used. On account of this requirement, the integer-N frequency synthesizer is not applicable to a system which requires a fast setting time below several microseconds.
Conventional frequency synthesizers include a fractional-N frequency synthesizer, in addition to the integer-N frequency synthesizer. The fractional-N frequency synthesizer mostly uses a multi-bit modulator or a MASH-type modulator. In general, the fractional-N frequency synthesizer is implemented in the form of a phase-locked-loop (PLL) including a modulator.
FIG. 1 is a circuit diagram showing a MASH-type modulator applied to a conventional fractional-N frequency synthesizer. Particularly, FIG. 1 depicts a 4th MASH modulator. Referring to FIG. 1, the 4th MASH modulator includes adders 100a through 100d, delay elements 120a through 120c, and accumulators 140a through 140d. 
An integer part input signal N(k) denotes an input signal relating to an integer pan in a division ratio. The integer part input signal N(k) is input to the adder 100a and added with the output of the adder 100b to thus generate a final division ratio signal Ndiv(k). A fractional part input signal f(k) denotes a fractional part in the division ratio, that is, denotes an input signal relating to the division ratio below the radix point. The fractional part input signal f(k) is accumulated at the accumulators 140a through 140d connected in series. The output of each accumulator 140a through 140d is fed to the input x of the next accumulator 140a through 140d. The overflows ovfl output from the respective accumulators 140a through 140d are added at the adders 100b, 100c, and 100d. For instance, the adder 100d adds the overflows of the accumulator 140d and the accumulator 140c, and delays the resultant value by the output of the delay element 120c, that is, subtracts a certain delay value from the overflow of the accumulator 140d. The subtracted value is fed into the adder 100c. The other adders 100c and 100b operate in the similar manner. The output s of the adder 100b can be a combination component of signal and noise.
The fractional-N frequency synthesizer using the MASH modulator as shown in FIG. 1 features a fast setting time. However, disadvantageously, a phase noise increases around 1 MHz and a satisfactory performance is not shown when obtaining an accurate resolution at 10 kHz. In reference to a paper entitled “A 1.1 GHz CMOS Fractional-N Frequency Synthesizer with a 3b 3rd-Order ΣΔ Modulator” by W. Rhee, A. All, and B. Song, ISSCC (International Solide-State Circuit Conference) 2000, pp. 198-1008, it is difficult to apply a fractional-N frequency synthesizer using a multi-bit modulator to actual mobile terminal systems because such a frequency synthesizer suffers large spurs about −40 dB at a particular condition. In other words, the multi-bit modulator or the MASH modulator requires high linearity according to operational characteristics of the PLL. Yet, in practice, the PLL cannot show the required high linearity due to nonlinearity resulted from a phase frequency detector or a multi-modulus divider therein.
U.S. Pat. No. 6,107,947 discloses a 3rd sigma-delta modulator which disadvantageously increases complexity. A sigma-delta modulator disclosed in U.S. Pat. No. 5,742,246 also increases complexity as well. Thus, a demand arises for a novel frequency synthesizer for resolving the above-mentioned disadvantages.